Field of the Disclosure
Embodiments of the present disclosure generally relate to semiconductor processing. More specifically, embodiments of the disclosure relate to a method for plasma-enhanced chemical vapor deposition (PECVD) lithography overlay.
Description of the Related Art
In the manufacture of integrated circuits (IC), or chips, patterns representing different layers of the chip are created by a chip designer. A series of reusable masks, or photomasks, are created from these patterns in order to transfer the design of each chip layer onto a semiconductor substrate during the manufacturing process. Mask pattern generation systems use precision lasers or electron beams to image the design of each layer of the chip onto a respective mask. The masks are then used much like photographic negatives to transfer the circuit patterns for each layer onto a semiconductor substrate. These layers are built up using a sequence of processes and translate into the tiny transistors and electrical circuits that comprise each completed chip. Typically, devices on semiconductor substrates are manufactured by a sequence of lithographic processing steps in which the devices are formed from a plurality of overlying layers, each having an individual pattern. Generally, a set of 15 to 100 masks is used to construct a chip and can be used repeatedly.
Between one layer and the next layer that overlays the one layer, the individual patterns of the one layer and the next layer must be aligned. However, due to pattern and material differences in the multiple overlying layers, film stress and/or topography variations (or pattern related differences) between layers are inevitable. The generated film stress between the layers formed on the substrate will cause the substrate to deform, which can lead to device yield issues for the semiconductor devices formed on the substrate. The residual stress may be created during substrate processing steps due to differences in thermal expansion, plasma non-uniformity distribution and/or plasma density during a plasma etching or plasma deposition processes, which results in the localized deformation of the substrate surface and leads to undesirable overlay error. When overlay errors, or pattern displacement undesirably occurs, the size, dimension or structures of device dies formed on the substrate may be irregularly deformed or distorted, thus increasing likelihood of misalignment between the film layers stacked thereon that may adversely increase the probability of misalignment in the subsequent lithographic exposure process.
Therefore, since the localized curvature formed in a substrate can have a dramatic effect on the ability to reliably form the next generation of semiconductor devices, which have smaller device feature sizes, there is a need for a system and method for detecting the localized deformation of a semiconductor substrate which can be used to adjust or correct the localized deformation in the substrate.